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? semiconductor components industries, llc,2004 october, 2004 ? rev. 10 1 publication order number: MC100EP196/d MC100EP196 3.3vecl programmable delay chip with ftune the MC100EP196 is a programmable delay chip (pdc) designed primarily for clock deskewing and timing adjustment. it provides variable delay of a differential necl/pecl input transition. it has similar architecture to the ep195 with the added feature of further tuneability in delay using the ftune pin. the ftune input takes an analog voltage from v cc to v ee to fine tune the output delay from 0 to 60 ps. the delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, figure 2. the delay increment of the ep196 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. the required delay is selected by the 10 data select inputs d[9:0] values and controlled by the len (pin 10). a low level on len allows a transparent load mode of real time delay values by d[9:0]. a low to high transition on len will lock and hold current values present against any subsequent changes in d[10:0]. the approximate delay values for varying tap numbers correlating to d0 (lsb) through d9 (msb) are shown in table 5. because the ep196 is designed using a chain of multiplexers, it has a fixed minimum delay of 2.4 ns. an additional pin, d10, is provided for controlling pins 14 and 15, cascade and cascade , also latched by len, in cascading multiple pdcs for increased programmable range. the cascade logic allows full control of multiple pdcs. switching devices from all a1o states on d[0:9] with setmax low to all a0o states on d[0:9] with setmax high will increase the delay equivalent to ad0o, the minimum increment. select input pins, d[10:0], may be threshold controlled by combinations of interconnects between v ef (pin 7) and v cf (pin 8) for lvcmos, ecl, or lvttl level signals. lvttl and lvcmos operation is available in pecl mode only. for lvcmos input levels, leave v cf and v ef open. for ecl operation, short v cf and v ef (pins 7 and 8). for lvttl level operation, connect a 1.5 v supply reference to v cf and leave open v ef pin. the 1.5 v reference voltage to v cf pin can be accomplished by placing a 2.2 k resistor between v cf and v ee for 3.3 v power supply. the v bb pin, an internally generated voltage supply, is available to this device only. for single?ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? maximum frequency > 1.2 ghz typical ? programmable range: 0 ns to 10 ns ? delay range: 2.4 ns to 12.4 ns ? 10 ps increments ? pecl mode operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ?3.0 v to ?3.6 v ? open input default state ? safety clamp on inputs ? a logic high on the en pin will force q to logic low ? d[10:0] can accept either ecl, lvcmos, or lvttl inputs ? v bb output reference voltage 32 1 mc100 awlyyww ep196 lqfp?32 fa suffix case 873a marking diagram* a = assembly location wl = wafer lot yy = year ww = work week *for additional marking information, refer to application note and8002/d. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information
MC100EP196 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 figure 1. 32?lead lqfp pinout (top view) v ee d0 v cc qq ftune v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf MC100EP196
MC100EP196 http://onsemi.com 3 table 1. pin description pin name i/o default state description 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 d[0:9] lvcmos, lvttl, ecl input low single?ended parallel data inputs [0:9]. internal 75 k to v ee . (note 1) 3 d[10] lvcmos, lvttl, ecl input low single?ended cascade/cascade control input. internal 75 k to v ee . (note 1) 4 in ecl input low noninverted differential input. internal 75 k to v ee . 5 in ecl input high inverted differential input. internal 75 k to v ee and 36.5 k to v cc . 6 v bb ? ? ecl reference voltage output 7 v ef ? ? reference voltage for ecl mode connection 8 v cf ? ? lvcmos, ecl, or lvttl input mode select 9, 28 v ee ? ? negative supply voltage. all v ee pins must be externally con- nected to power supply to guarantee proper operation. (note 2) 13, 18, 19, 22 v cc ? ? positive supply voltage. all v cc pins must be externally con- nected to power supply to guarantee proper operation. (note 2) 10 len ecl input low single?ended d pins load / hold input. internal 75 k to v ee . 11 setmin ecl input low single?ended minimum delay set logic input. internal 75 k to v ee . (note 1) 12 setmax ecl input low single?ended maximum delay set logic input. internal 75 k to v ee . (note 1) 14 cascade ecl output ? inverted differential cascade output for d[10] input. typically ter- minated with 50 to v tt = v cc ? 2 v. 15 cascade ecl output ? noninverted differential cascade output for d[10] input. typically terminated with 50 to v tt = v cc ? 2 v. 16 en ecl input low single?ended output enable pin. internal 75 k to v ee . 17 ftune analog input ? fine tuning input. 21 q ecl output ? noninverted differential output. typically terminated with 50 to v tt = v cc ? 2 v. 20 q ecl output ? inverted differential output. typically terminated with 50 to v tt = v cc ? 2 v. 1. setmin will override setmax if both are high. setmax and setmin will override all d[0:10] inputs. 2. all v cc and v ee pins must be externally connected to power supply to guarantee proper operation.
MC100EP196 http://onsemi.com 4 table 2. control pin pin state function en low (note 3) input signal is propagated to the output high output holds logic low state len low (note 3) transparent or load mode for real time delay values present on d[0:10]. high lock and hold mode for delay values on d[0:10]; further changes on d[0:10] are not recognized and do not affect delay. setmin low (note 3) output delay set by d[0:10] high set minimum output delay setmax low (note 3) output delay set by d[0:10] high set maximum output delay d10 low cascade output low, cascade output high high cascade output low, cascade output high 3. internal pulldown resistor will provide a logic low if pin is left unconnected. table 3. control d[0:10] interface pin state function v cf v ef pin (note 4) ecl mode v cf no connect lvcmos mode v cf 1.5 v 100 mv lvttl mode (note 5) 4. short v cf (pin 8) and v ef (pin 7). 5. when operating in lvttl mode, the reference voltage can be provided by connecting an external resistor, r cf (suggested resistor value is 2.2 k 5%), between v cf and v ee pins. table 4. data input allowed operating voltage mode table control data select inputs pins (d [0:10]) power supply lvcmos lvttl lvpecl lvnecl pecl mode operating range yes yes yes n/a necl mode operating range n/a n/a n/a yes
MC100EP196 http://onsemi.com 5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 in in 512 gd* 0 1 256 gd* 0 1 128 gd* 0 1 64 gd* 0 1 32 gd* 0 1 16 gd* 0 1 8 gd* 0 1 4 gd* 0 1 2 gd* 0 1 1 gd* 0 1 1 gd* 0 1 1 gd* 0 1 latch cascade cascade q q en len set min set max 10 bit latch d10 *gd = (gate delay) approximately 10 ps delay per gate (fixed minimum delay approx. 2.4 ns) v bb v cf v ef figure 2. logic diagram v ee ftune
MC100EP196 http://onsemi.com 6 table 5. theoretical delta delay values d(9:0) value setmin setmax programmable delay* xxxxxxxxxx h l 0 ps 0000000000 l l 0 ps 0000000001 l l 10 ps 0000000010 l l 20 ps 0000000011 l l 30 ps 0000000100 l l 40 ps 0000000101 l l 50 ps 0000000110 l l 60 ps 0000000111 l l 70 ps 0000001000 l l 80 ps 0000010000 l l 160 ps 0000100000 l l 320 ps 0001000000 l l 640 ps 0010000000 l l 1280 ps 0100000000 l l 2560 ps 1000000000 l l 5120 ps 1111111111 l l 10230 ps xxxxxxxxxx l h 10240 ps *fixed minimum delay not included. table 6. typical ftune delay pin input range output range v cc ?v ee (v) 0 ? 60 (ps)
MC100EP196 http://onsemi.com 7 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000 0 100 200 300 400 500 600 700 800 900 1000 delay ( ps) decimal value of select inputs (d[9:0]) 85 c 25 c ?40 c figure 3. measured delay vs. select inputs table 7. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity (note 1) level 2 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 1237 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
MC100EP196 http://onsemi.com 8 table 8. maximum ratings symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ?6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ?6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm lqfp?32 lqfp?32 80 55 c/w c/w jc thermal resistance (junction?to?case) standard board lqfp?32 12 to 17 c/w t sol wave solder < 2 to 3 sec @ 248 c 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected.
MC100EP196 http://onsemi.com 9 table 9. dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 2) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 125 160 110 130 170 110 135 175 ma v oh output high voltage (note 3) 2155 2300 2405 2155 2300 2405 2155 2300 2405 mv v ol output low voltage (note 3) 1355 1520 1605 1355 1500 1605 1355 1485 1605 mv v ih input high voltage (single?ended) lvpecl lvcmos lvttl 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 mv v il input low voltage (single?ended) lvpecl lvcmos lvttl 1355 0 0 1675 800 800 1355 0 0 1675 800 800 1355 0 0 1675 800 800 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v cf lvttl mode input detect voltage @ iv cf = 700 a 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 v v ef reference voltage for ecl mode connection 1900 1960 2050 1875 1953 2050 1850 1945 2050 mv v ihcmr input high voltage common mode range (differential) (note 4) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current (pecl) in, in , en , len, setmin, setmax 150 150 150 a i ihh ftune input high current @ v cc 50 87 150 50 84 150 50 82 150 a i il input low current (pecl) in, in , en , len, setmin, setmax 0.5 0.5 0.5 a i ill ftune input low current @v ee ?10 0 10 ?10 0 10 ?10 0 10 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?0.3 v. 3. all loading with 50 to v cc ? 2.0 v. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
MC100EP196 http://onsemi.com 10 table 10. dc characteristics, necl v cc = 0 v, v ee = ?3.3 v (note 5) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 100 125 160 110 130 170 110 135 175 ma v oh output high voltage (note 6) ?1145 ?1000 ?895 ?1145 ?1000 ?895 ?1145 ?1000 ?895 mv v ol output low voltage (note 6) ?1945 ?1780 ?1695 ?1945 ?1800 ?1695 ?1945 ?1815 ?1695 mv v ih input high voltage (single?ended) lvnecl ?1225 ?880 ?1225 ?880 ?1225 ?880 mv v il input low voltage (single?ended) lvnecl ?1945 ?1625 ?1945 ?1625 ?1945 ?1625 mv v bb output voltage reference ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 ?1525 ?1425 ?1325 mv v ef reference voltage for ecl mode connection ?1400 ?1340 ?1250 ?1425 ?1347 ?1250 ?1450 ?1355 ?1250 mv v ihcmr input high voltage common mode range (differential) (note 7) v ee +2.0 0 v ee +2.0 0 v ee +2.0 0 v i ih input high current in, in , en , len, setmin, setmax 150 150 150 a i ihh ftune input high current @ v cc 50 87 150 50 84 150 50 82 150 a i il input low current in, in , en , len, setmin, setmax 0.5 0.5 0.5 a i ill ftune input low current @ v ee ?10 0 10 ?10 0 10 ?10 0 10 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to ?0.3 v. 6. all loading with 50 to v cc ? 2.0 v. 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
MC100EP196 http://onsemi.com 11 table 11. ac characteristics v cc = 0 v; v ee = ?3.0 v to ?3.6 v or v cc = 3.0 v to 3.6 v; v ee = 0 v (note 8) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency 1.2 1.2 1.2 ghz t plh t phl propagation delay in to q; d(0?9) = 0 in to q; d(0?9) = 1023 en to q; d(0?9) = 0 d10 to cascade 1810 9500 1780 350 2210 11496 2277 450 2610 13500 2780 550 1960 10000 1930 380 2360 12258 2430 477 2760 14000 2930 580 2180 10955 2150 420 2580 13454 2650 520 2980 15955 3150 620 ps t range programmable range {d(0?9) = hi} ? {d(0?9) = lo} 8600 9285 10000 9200 9897 10700 9900 10875 12000 ps t step delay (note 9) d0 high d1 high d2 high d3 high d4 high d5 high d6 high d7 high d8 high d9 high 90 245 530 1060 2160 4335 7 23 39 58 137 293 590 1158 2317 4647 185 335 650 1265 2490 5010 100 260 560 1130 2290 4590 11 30 48 67 149 313 629 1237 2472 4955 200 370 710 1355 2680 5385 90 270 600 1200 2450 4935 13 32 53 73 154 337 681 1353 2712 5440 225 410 770 1520 3015 6015 ps mono monotonicity (note 10) 9 10 11 ps t skew duty cycle skew (note 11) |t phl ?t plh | 20 22 27 ps t s setup time d to len d to in (note 12) en to in (note 13) 150 100 150 ?10 ?130 ?105 150 100 150 ?70 ?150 ?120 150 100 150 ?70 ?165 ?140 ps t h hold time len to d in to en (note 14) 225 450 170 275 200 450 70 305 200 450 60 325 ps t r release time en to in (note 15) set max to len set min to len 150 400 300 ?105 70 165 150 400 350 ?120 110 180 150 400 350 ?140 160 205 ps t jit random clock jitter @ 1.2 ghz, setmax delay 3 3 3 ps v pp input voltage swing (differential) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall time 20?80% (q) 20?80% (cascade) 85 100 110 150 130 200 95 110 120 160 145 210 110 125 135 175 160 225 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. 9. specification limits represent the amount of delay added with the assertion of each individual delay control pin. the various combinations of asserted delay control inputs will typically realize d0 resolution steps across the specified programmable range. 10. the monotonicity indicates the increased delay value for each binary count increment on the control inputs d(0?9). 11. duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 12. this setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 13. this setup time is the minimum time that en must be asserted prior to the next transition of in/in to prevent an output response greater than v cc ? 1425 mv to that in/in transition. 14. this hold time is the minimum time that en must remain asserted after a negative going in or positive going in to prevent an output response greater than v cc ? 1425 mv to that in/in transition. 15. this release time is the minimum time that en must be deasserted prior to the next in/in transition to ensure an output response that meets the specified in to q propagation delay and transition times.
MC100EP196 http://onsemi.com 12 figure 4. ac reference measurement in in q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) using the ftune analog input the analog ftune pin on the ep196 device is intended to add more delay in a tunable gate to enhance the 10 ps resolution capabilities of the fully digital ep196. the level of resolution obtained is dependent on the voltage applied to the ftune pin. to provide this further level of resolution, the ftune pin must be capable of adjusting the additional delay finer than the 10 ps digital resolution (see logic diagram). this requirement is easily achieved because a 60 ps additional delay can be obtained over the entire ftune voltage range (see figure 5). this extra analog range ensures that the ftune pin will be capable even under worst case conditions of covering a digital resolution. typically, the analog input will be driven by an external dac to provide a digital control with very fine analog output steps. the final resolution of the device will be dependent on the width of the dac chosen. to determine the voltage range necessary for the ftune input, figure 5 should be used. there are numerous voltage ranges which can be used to cover a given delay range; users are given the flexibility to determine which one best fits their designs. figure 5. typical ep196 delay versus ftune voltage ftune voltage (v) ?3.3 ?2.97 ?2.64 ?2.31 ?1.98 ?1.65 ?1.32 ?0.99 ?0.66 ?0.33 0 90 80 70 60 50 40 30 20 10 0 ?10 delay (ps) ?40 c 85 c 25 c v cc = 0 v v ee = ?3.3 v v cc v ee
MC100EP196 http://onsemi.com 13 cascading multiple ep196s to increase the programmable range of the ep196, internal cascade circuitry has been included. this circuitry allows for the cascading of multiple ep196s without the need for any external gating. furthermore, this capability requires only one more address line per added e196. obviously, cascading multiple programmable delay chips will result in a larger programmable range; however, this increase is at the expense of a longer minimum delay. figure 6 illustrates the interconnect scheme for cascading two ep196s. as can be seen, this scheme can easily be expanded for larger ep196 chains. the d10 input of the ep196 is the cascade control pin and when assert high switches output pin cascade to high and pin cascade to low. with the interconnect scheme of figure 6 when d10 is asserted, it signals the need for a larger programmable range than is achievable with a single device. the a11 address can be added to generate a cascade output for the next ep196. for a 2?device configuration, a11 is not required. figure 6. cascading interconnect architecture v ee d0 v cc q q ftune v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf input output ep196 chip #2 ep196 chip #1 address bus a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 need if chip #3 is used dac v ee d0 v cc q q ftune v cc v cc cascade en setmax v cc v ee len d2 d1 cascade setmin v bb in v ee d8 v ef d3 d4 d5 d6 d7 d9 d10 in v cf
MC100EP196 http://onsemi.com 14 an expansion of the latch section of the block diagram is pictured in figure 7. use of this diagram will simplify the explanation of how the setmin and setmax circuitry works in cascade. when d10 of chip #1 in figure 5 is low, this device's cascade output will also be low while the cascade output will be high. in this condition, the setmin pin of chip #2 will be asserted high and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. chip #1, on the other hand, will have both setmin and setmax deasserted so that its delay will be controlled entirely by the address bus a0?a9. if the delay needed is greater than can be achieved with 1023 gate delays (1111111111 on the a0?a9 address bus), d10 will be asserted to signal the need to cascade the delay to the next ep196 device. when d10 is asserted, the setmin pin of chip #2 will be deasserted and the setmax pin asserted, resulting in the device delay to be the maximum delay. table 12 shows the delay time of two ep196 chips in cascade. to expand this cascading scheme to more devices, one simply needs to connect the d10 pin from the next chip to the address bus and cascade outputs to the next chip in the same manner as pictured in figure 6. the only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. furthermore, to fully utilize ep196, the ftune pin can be used for additional delay and for finer resolution than 10 ps. as shown in figure 5, an analog voltage input from dac can adjust the ftune pin with an extra 60 ps of delay for each chip. set min set max to select multiplexers bit 0 d0 q0 len set reset figure 7. expansion of the latch section of the ep196 block diagram bit 1 d1 q1 len set reset bit 2 d2 q2 len set reset bit 3 d3 q3 len set reset bit 4 d4 q4 len set reset bit 5 d5 q5 len set reset bit 6 d6 q6 len set reset bit 7 d7 q7 len set reset bit 8 d8 q8 len set reset bit 9 d9 q9 len set reset
MC100EP196 http://onsemi.com 15 table 12. cascaded delay value of two ep196s variable input to chip #1 and setmin for chip #2 input for chip #1 total d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 delay value delay value 0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps 0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps 0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps 0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps 0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps 0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps 0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps 0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps 0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps 0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps 0 0 0 0 0 1 0 0 0 0 0 320 ps 4720 ps 0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps 0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps 0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps 0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps 0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps variable input to chip #1 and setmax for chip #2 input for chip #1 total d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 delay value delay value 1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps 1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps 1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps 1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps 1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps 1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps 1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps 1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps 1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps 1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps 1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps 1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps 1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps 1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps 1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps 1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps
MC100EP196 http://onsemi.com 16 multi?channel deskewing the most practical application for ep196 is in multiple channel delay matching. slight differences in impedance and cable length can create large timing skews within a high?speed system. to deskew multiple signal channels, each channel can be sent through each ep196 as shown in figure 8. one signal channel can be used as reference and the other ep196s can be used to adjust the delay to eliminate the timing skews. nearly any high?speed system can be fine tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances using the available ftune pin. figure 8. multiple channel deskewing diagram ep196 in q in q #1 ep196 in q in q #2 ep196 in q in q #n digital data control logic dac
MC100EP196 http://onsemi.com 17 figure 9. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping 2 MC100EP196fa lqfp?32 250 units / tray MC100EP196far2 lqfp?32 2000 / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
MC100EP196 http://onsemi.com 18 resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1642/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
MC100EP196 http://onsemi.com 19 package dimensions detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ?t? ?z? ?u? t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t-u m 0.20 (0.008) z ac 32 lead lqfp case 873a?02 issue b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
MC100EP196 http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MC100EP196/d eclinps is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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